Intel introduces an approach to boost the power-efficiency and reliability of packaged chiplet ecosystems
Cred­it: Das Shar­ma et al

The inte­gra­tion of elec­tron­ic chips in com­mer­cial devices has sig­nif­i­cant­ly evolved over the past decades, with engi­neers devis­ing var­i­ous inte­gra­tion strate­gies and solu­tions. Ini­tial­ly, com­put­ers con­tained a cen­tral proces­sor or cen­tral pro­cess­ing unit (CPU), con­nect­ed to mem­o­ry units and oth­er com­po­nents via tra­di­tion­al com­mu­ni­ca­tion path­ways, known as front-side-bus (FSB) inter­faces.

Tech­no­log­i­cal advances, how­ev­er, have enabled the devel­op­ment of new inte­grat­ed cir­cuit (IC) archi­tec­tures rely­ing on mul­ti­ple chiplets and more sophis­ti­cat­ed elec­tron­ic com­po­nents. Intel Cor­po­ra­tion played a cru­cial role in these devel­op­ments, by intro­duc­ing new archi­tec­tures and spec­i­fi­ca­tions for the design of sys­tems with mul­ti­ple pack­aged chiplets.

Researchers at Intel Cor­po­ra­tion San­ta Clara recent­ly out­lined a new vision for fur­ther boost­ing the per­for­mance of sys­tems devel­oped fol­low­ing uni­ver­sal chiplet inter­con­nect express (UCIe), a spec­i­fi­ca­tion to stan­dard­ize the con­nec­tions between mul­ti-func­tion chiplets in mod­ern Sys­tem-in-Pack­age (SiP). Their pro­posed approach, pre­sent­ed in a paper in Nature Elec­tron­ics, entails reduc­ing the fre­quen­cy in these cir­cuits to boost their pow­er effi­cien­cy and per­for­mance.

“We have been dri­ving tech­nolo­gies, such as PCI-Express, CXL, and UCIe, that are mul­ti-gen­er­a­tional,” Dr. Deben­dra Das Shar­ma, Intel Senior Fel­low and co-GM of Mem­o­ry and I/O Tech­nolo­gies, Data Plat­forms and Arti­fi­cial Intel­li­gence Group at Intel Cor­po­ra­tion, told Tech Xplore. “In the con­text of UCIe, after com­plet­ing UCIe 1.0, we have been look­ing at how to deliv­er anoth­er order or two more per­for­mance with ide­al­ly an order low­er pow­er per bit to meet the insa­tiable demand for pow­er-effi­cient per­for­mance.”

Advances in the devel­op­ment of sil­i­con and pack­ag­ing tech­nol­o­gy have opened new pos­si­bil­i­ties for reduc­ing the spac­ing between the bumps that con­nect indi­vid­ual chips with­in cir­cuit boards, also known as bump pitch­es. The pri­ma­ry objec­tive of the study by Dr. Das Shar­ma and his col­lab­o­ra­tors was to explore strate­gies that would allow researchers to fur­ther boost the per­for­mance and pow­er effi­cien­cy of sys­tems as these bump pitch­es con­tin­ue to be reduced for on-pack­age inter­con­nects.

“The trend in advanced pack­ag­ing, includ­ing 3D, is reduced bump pitch,” Dr. Das Shar­ma said. “Bump pitch is the min­i­mum dis­tance between two bumps that will con­nect two chiplets. So, that means we get more wires between two chiplets as the bump pitch reduces. The nat­ur­al ten­den­cy, pri­mar­i­ly borne out of exter­nal inter­con­nects, is to push the fre­quen­cy high­er. How­ev­er, in this case, since the num­ber of wires increas­es, we need to push the fre­quen­cy low­er to make the cir­cuits fit and get low­er pow­er.”

As part of their study, Dr. Das Shar­ma and his col­leagues car­ried out analy­ses to fur­ther explore the effects of reduc­ing the fre­quen­cy in sys­tems based on pack­aged chiplets. They found that con­trary to tra­di­tion­al chip con­nec­tiv­i­ty inter­faces, UCIe-aligned tech­nolo­gies sig­nif­i­cant­ly ben­e­fit­ted from a reduc­tion in fre­quen­cy as bump inter­con­nect pitch­es were reduced.

Specif­i­cal­ly, reduc­tions in fre­quen­cy were found to improve both the sys­tems’ pow­er effi­cien­cy and their over­all per­for­mance. Over­all, this recent paper thus iden­ti­fies a new valu­able approach that could con­tribute to the future advance­ments of sys­tems with inter­con­nect­ed cir­cuits as their under­ly­ing archi­tec­ture evolves fur­ther.

“We hope that the broad indus­try can ben­e­fit from our work through stan­dard­iza­tion the same way we have done in the past influ­enc­ing indus­try stan­dard spec­i­fi­ca­tions,” Dr. Das Shar­ma added. “Per­son­al­ly, I now plan to con­tin­ue to work to evolve indus­try stan­dard inter­con­nects like UCIe, CXL, PCIe as I have done for more than two decades. In the con­text of chiplets and UCIe, the jour­ney has just start­ed and I am excit­ed about the oppor­tu­ni­ties ahead of us.”

More infor­ma­tion:
Deben­dra Das Shar­ma et al, High-per­for­mance, pow­er-effi­cient three-dimen­sion­al sys­tem-in-pack­age designs with uni­ver­sal chiplet inter­con­nect express, Nature Elec­tron­ics (2024). DOI: 10.1038/s41928-024–01126‑y

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Intel intro­duces approach to boost pow­er effi­cien­cy, reli­a­bil­i­ty of pack­aged chiplet ecosys­tems (2024, March 13)
retrieved 3 April 2024

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